ADE7518
POWER SUPPLY ARCHITECTURE
The ADE7518 has two power supply inputs, V DD and V BAT , and
requires only a single 3.3 V power supply at V DD for full operation.
A battery backup, or secondary power supply, with a maximum
of 3.7 V, can be connected to the V BAT input. Internally, the
ADE7518 connects V DD or V BAT to V SWOUT , which is used to derive
power for the ADE7518 circuitry. The V SWOUT output pin reflects
the voltage at the internal power supply (V SWOUT ) and has a
maximum output current of 6 mA. This pin can also be used
to power a limited number of peripheral components. The 2.5 V
analog supply (V INTA ) and the 2.5 V supply for the core logic
(V INTD ) are derived by on-chip linear regulators from V SWOUT .
Figure 27 shows the power supply architecture of ADE7518.
The ADE7518 provides automatic battery switchover between
V DD and V BAT based on the voltage level detected at V DD or V DCIN .
The battery switchover functionality provided by the ADE7518
allows a seamless transition from V DD to V BAT . An automatic
battery switchover option ensures a stable power supply to the
ADE7518, as long as the external battery voltage is above 2.75 V.
It allows continuous code execution even while the internal
power supply is switching from V DD to V BAT and back. Note that
the energy metering ADCs are not available when V BAT is being
used for V SWOUT .
Power supply management (PSM) interrupts can be enabled to
indicate when battery switchover occurs and when the V DD
power supply is restored (see the Power Supply Management
(PSM) Interrupt section).
V DD to V BAT
The following three events switch the internal power supply
(V SWOUT ) from V DD to V BAT :
Additionally, the BCTRL input can be used to trigger a battery
switchover. The conditions for switching V SWOUT from V DD to
V BAT and back to V DD are described in the Battery Switchover
section. V DCIN is an input pin that can be connected to a 0 V to
3.3 V dc signal. This input is intended for power supply super-
visory purposes and does not provide power to the ADE7518
circuitry (see the Battery Switchover section).
V DCIN V DD V BAT V SWOUT
?
?
V DCIN < 1.2 V. When V DCIN falls below 1.2 V, V SWOUT switches
from V DD to V BAT . This event is enabled when the
BATPRG[1:0] bits in the Battery Switchover Configuration
SFR (BATPR, 0xF5) = 0b01. Setting these bits disables
switchover based on V DCIN . Battery switchover on low
V DCIN is disabled by default.
V DD < 2.75 V. When V DD falls below 2.75 V, V SWOUT switches
from V DD to V BAT . This event is enabled when BATPRG[1:0] in
LDO
V INTD
MCU
?
the BATPR SRF are cleared.
Falling edge on BCTRL. When the battery control pin,
BCTRL
POWER SUPPLY
MANAGEMENT
V SW
LDO
V INTA
ADE
BCTRL, goes low, V SWOUT switches from V DD to V BAT . This
external switchover signal can trigger a switchover to V BAT
at any time. Setting the bits INT1PRG[2:0] to 0bx01 in the
SPI/I 2 C
Interrupt Pins Configuration SFR (INTPR, 0xFF) enables
SCRATCHPAD
LCD
RTC
UART
the battery control pin (see Table 15).
Switching from V BAT to V DD
3.3V
Figure 27. Power Supply Architecture
2.5V
To switch V SWOUT from V BAT to V DD , all of the following events
that are enabled to force battery switchover must be false:
BATTERY SWITCHOVER
The ADE7518 monitors V DD , V BAT , and V DCIN . Automatic battery
switchover from V DD to V BAT can be configured based on the
status of the V DD , V DCIN , or BCTRL pin. Battery switchover is
enabled by default. Setting Bit 1 in the Battery Switchover Configu-
ration SFR (BATPR, 0xF5) disables battery switchover so that
V DD is always connected to V SWOUT (see Table 17). The source of
?
?
?
V DCIN < 1.2 V and V DD < 2.75 V enabled. If the low V DCIN
condition is enabled, V SWOUT switches to V DD after V DCIN
remains above 1.2 V and V DD remains above 2.75 V.
V DD < 2.75 V enabled. V SWOUT switches back to V DD after
V DD remains above 2.75 V.
BCTRL enabled. V SWOUT switches back to V DD after BCTRL
is high, and the first or second bullet point is satisfied.
V SWOUT is indicated by Bit 6 in the Peripheral Configuration SFR
(PERIPH, 0xF4), which is described in Table 18. Bit 6 is set
when V SWOUT is connected to V DD and cleared when V SWOUT is
connected to V BAT .
Rev. 0 | Page 25 of 128
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